Explorations in Low Area Overhead DfT Techniques for Sequential BIST
نویسندگان
چکیده
The paper proposes a new, low area overhead Designfor-Testability (DfT) technique of Built-In Self-Test (BIST) for sequential circuits. The technique is based on making the status signals entering the control part controllable during the test mode. This requires a simple controller to manipulate these signals in order to force the device under test to traverse all the branches in the FSM state transition graph. Experimental results carried out on six different sequential examples show that the number of signals to be controlled (usually 1-2 bits), and thus the extra silicon area, is very low. In addition, the experiments show that the optimal BIST solution for a design is highly dependent on its testability characteristics.
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